New IC Carrier Plating Process: Blind Hole, Through Hole and Embedded Groove Filling
In the era of miniaturization of electronic products, high yield and low-cost integrated circuit (IC) boards can realize high-density interconnection (HDI) between chips and circuit boards by reliable methods. In order to maximize the available space of the carrier plate, the distance between copper wires should be minimized, i.e. line width and line spacing (L/S). In common PCB technology, the line width and line spacing are larger than 40 microns, while the more advanced wafer-level technology can reach 2 microns at present. Over the past decade, chip size has decreased significantly with L/S on board, which poses unique challenges to both printed circuit and semiconductor industries.
Process performance of blind hole filling and through hole plating by enhanced pattern plating
Embedded groove filling performance, showing a high degree of consistency between pad and wiring
Fan-out Panel-level Packaging (FOPLP) is a new manufacturing technology aimed at narrowing the gap between PCB and IC/Semiconductor. Although FOPLP is still an emerging technology, it can improve area utilization and productivity, and enhance competitive advantage by reducing costs, so it is very popular in the market. In this market, the key to ensure the performance of fine circuits is the uniformity or smoothness of plating.
Uniformity of plating, smoothness of top of line/blind hole (measuring smoothness of top of line) and blind hole are the characteristics of its performance. It is particularly important in multi-layer circuit fabrication because the inhomogeneity of the lower l ayer may affect the subsequent plating, thus destroying device design and leading to disastrous consequences such as short circuit. In addition, the uneven surface will make the connection points (i.e. blind holes and routes) distort, resulting in signal transmission loss. Therefore, it is the industry's expectation that the electroplating solution with uniform and even contour can be provided without any special post-processing.
Schematic diagram of CEAC mechanism (green represents inhibitor, red represents leveler, yellow represents brightener)
The innovative composite additive for DC copper plating on IC carrier can be used to fill embedded grooves by improved graphic plating, and to fill through and blind holes in the plating process at the same time. These new products can not only form better alignment profile, but also fill blind holes and electroplating through holes.