[PCB Design] Vertical Conductor Structure: Allegro PCB Editor

In the field of PCB design, with the increasing design density and complexity, sometimes designers need to use different via technology to route devices with a large number of pins, while at the same time ensuring the highest level of signal integrity. Using through holes can take up a lot of valuable board space. However, although the use of smaller blind holes can reduce the size of the vias, it requires larger buried holes to complete the connection at the deeper positions of the circuit board. Another costly alternative is to use any layer interconnect (ELIC) technology, which means that each pair of layers has its own microvias, which are drilled with lasers And filled with copper. Stacking these micro-vias on top of each other on the surface between each pair of layers can extend the connection between any two layers in the circuit board. These through-hole technologies can successfully complete the layout of the design, but at the same time will increase the number of circuit board layers, which can cause signal integrity problems if not handled properly.

New vertical conductor structure (VeCS) technology reduces the number of layers and improves signal integrity without the need for sequential lamination. VeCS is different from traditional vias, micro vias, and ELIC designs. The latter three technologies are costly and require multiple lamination, drilling, and plating cycles to produce a reasonable number of layers. VeCS technology can be used to combine routing channels, making better use of channels to achieve fanout for devices with more pins. More routing channels allow for more routing under a more reliable / rugged planar reference without the problems typically found with other through-hole technologies. Visit https://www.nextgin-tech.com for more details on VeCS technology.

In Allegro 17.2, the VeCS structure is a mechanical symbol. It can be placed anywhere or in a ball grid array (BGA) device footprint to take advantage of this new routing fan-out technology. In addition to the production output upgrade, a limited depth (blind hole) drill file is generated for the pins to support the VeCS-2 blind depth structure. No major changes are required to support these new structures in Allegro PCB Designer. If these structures are used in the layout process, 17.2 Padstack Editor supports layer-by-layer and adjacent-layer forbidden areas to ensure product manufacturability. These structures can be created as library objects, so it is easy to take advantage of these structures when fanout routing common devices in many designs. If a structure needs to be changed, it only needs to be changed in one place. After refreshing, all other similar structures in the entire layout can be completely modified.

VeCS

Now let's distinguish between two "slot" technologies: VeCS-1 refers to the slot that runs through the entire circuit board, and VeCS-2 refers to the multilayer blind slot of the circuit board (see Figure 1).

Figure 1: The slot on the left front is VeCS-1 and the slot on the right is VeCS-2

In practical applications, we will mix VeCS-1 and VeCS-2 structures. The advantage is that we can use VeCS-1 to connect GND and power to multiple layers. For example, adjacent signals are only connected to layer 4. The VeCS-2 part in the slot will generate residual stake connections, which minimizes the capacitive reactance and dispersion of high-speed transmission signals.

Currently, NextGIn Technology focuses on next-generation products, such as UHF bandwidth applications. When the signal between two layers is transmitted from one layer and connected to the next layer, the impedance and signal of the vertical trace can be adjusted. The layer impedances match. Therefore, the transmission loss between the layers is minimized. Compared with the point-to-point wiring with low efficiency and high cost of the traditional via technology currently used, the new technology can make more efficient use of wiring space.

VeCS can be used in combination with through-hole, buried / blind, and micro-via / HDI technologies without any restrictions. For example, a VeCS core / multilayer can be sandwiched between a set of micro vias on the top and bottom of the board.

The current process flow is as follows:
1. Produce circuit boards according to standard processes
2. Slot formation (optional in the mechanical drilling phase): VeCS-1 and VeCS-2 structures are constructed by front and back drilling
3. Finish plating (standard)
4. Fill slots and holes (optional)
5. Form secondary milling and bottom milling
6. Fill the tank (secondary wiring)
7. Drilling through holes (optional)
8. Complete surface plating, similar to plated over-filled via (POFV)
9. Complete the panel according to the standard
 
Establish VeCS design rules

The rules applicable to VeCS are the same as those used in through / via technology or HDI technology. It is very important to set the parameters of the image overlap (hole ring) such as the overlap of the slot and copper, and the overlap of the second milling and slot.

Fig. 2 is a top view of VeCS elements, and changes in all vertical line widths of all elements of VeCS formed by secondary milling at different locations. Using this feature, we can create vertical traces with different impedances. Figure 2 also shows that the way the secondary wiring passes through the plating is different because solid copper (for example, forming a thick copper connection) is left over most of the groove perimeter.

 
Figure 2: Definition of VeCS parts

Table 1 shows the dimensions we are currently using. Although we are currently using the parameters for the standard size column, we will use the parameters for higher-order sizes in the near future. Before starting the design, be sure to check with the PCB board manufacturer to verify the feasibility of these values.
 
Table 1: VeCS-1 and VeCS-2 design guidelines
 
Pad definition

For the outer layer, or when using VeCS vertical routing, the general rule is that we need to confirm that the holes have plating. When determining the pad size, we need to consider that hole-making techniques can cause misalignment. In FIG. 3, the outer pad is represented by a rounded square and a rounded rectangle. As long as the rules are followed, circular pads or pads of any other shape are possible.

The A pad has an exposed plating layer, which will be removed by etching, resulting in an open circuit, or a connection break during assembly or use. The B pad covers the entire part of the plating layer and prevents the plating layer from being removed by etching.
 
 
Figure 3: Outer pad definition

For the inner layer, we have similar settings (Figure 4), and the rules are much simpler. We must ensure that we take into account the possible alignment errors caused by using pads to ensure the connection between the inner copper layer and the plating layer. We also need to allow enough overlap between the pad and the groove to compensate for misalignment and ensure that the pad will always contact the plating. Generally, half of the pads are milled off when the groove is formed. An example of reduced pad size shows that smaller pads are also possible, but like drilling, the pads may be pulled out during milling.
 
Figure 4: Definition of inner pads

In Figure 4, we used pads of different shapes and sizes. Choose the pad that suits you best, and not using a pad is also an option. When the widths of the horizontal and vertical traces are close, if the second milling and the inner layer are not consistent with the design margin, then small alignment errors may cause open circuits.

The inner layer does not have the problem of etching away the plating layer. The condition of pad A is valid. The only important thing is that the DRC function in the CAD system must take the plating layer into consideration, and usually the pad is the determining factor.

The size of the ring must be at least 0.1 mm to prevent the hole from breaking. Consult with the PCB board manufacturer before starting the design in accordance with the size / design rules. Non-functional pads can also be removed in VeCS designs.

In the following, we will explain how Cadence applied VeCS to the Allegro design system. Different from the design criteria described in the first part, we use secondary drilling for secondary milling. Where space permits, secondary drilling can be used.

Overview of VeCS Structure in Cadence Allegro System

In the Allegro Symbol Editor, pins and vias are used to generate VeCS structures into mechanical symbols. These mechanical symbols are then placed into the design for routing as needed, without the need to add VeCS structural symbols to the schematic. The standard VeCS structure can be constructed with through hole drilling features (VeCS-1) or blind hole drilling features (VeCS-2).

The following is a detailed description of the different entities in the VeCS structure (Figure 5):
Plating baths defined as pins
Pins without assigned logic pin numbers
· Non-plated tank separators defined as pins
Can be used for slots with finer pitch BGA pins
· Connection vias, defined as vias with stub traces
Once the end of the stub trace touches the center of the BGA pin, the via will use the BGA pin network.
In order to speed up the creation, the arrangement of the vias / stubs can be set in the layout, and then imported into the Symbol Editor using sub-graphics
Arrange different objects into the final VeCS structure
· Tip: The pad / drill size used for the pin / via is determined by the application in which it is designed (ie BGA pitch and solder ball pad size).
  
Figure 5: Different entities in VeCS structure

Pad stack generation (1mm BGA / 0.045mm solder ball pad)

Electroplating tank
· Electroplating tanks serve as the foundation for structures that are not directly connected to the grid (Figure 6)
Drilling = 5.254 mm x 0.254 mm
X size slot = BGA pad connection span + Y size slot
· Regular pad (all layers) / mask pad (outer layer) = 5.508 mm x 0.508 mm oval
Anti-pad = 5.127 mm x 0.127 mm oval
The size of the anti-pad should be smaller than the size of the drilled hole, so that the connection via can be attached to the slot wall of the negative film.
The anti-pad on the via is connected to the non-plated area of ​​the non-plated hole to isolate the unconnected position.
· Heat sink (all layers) = None
The plating tank is not directly connected, no heat dissipation is required
The forbidden area of ​​the adjacent layer = 5.508 mm x 0.508 mm oval
VeCS-2 Mechanical Drilling Overshoot Amplitude Clearance (Blind Depth)
· Placement of plating tank
Placed orthogonally between BGA solder ball pads (Figure 7)

Figure 6: Plating bath

Figure 7: Alignment with BGA pin footprint
 
Non-plated holes / slots (slot separators)
· Non-plated holes can be used to divide the slot into multiple parts so that independent connections can be made by passing through the slot wall (Figure 8)
Drilling = 0.559 mm
· Round with regular pads (all layers) = 0.127 mm
· Anti-pad / heat sink (all layers) = None
· Circle of restricted area (all layers) = 0.813 mm
· Circle of solder mask (outer layer) = 0.356 mm
Circle of the forbidden area of ​​the adjacent layer = 0.813 mm
VeCS-2 Overshoot Clearance for Mechanical Drilling (Blind Hole Depth)
· Placement of non-plated holes
Placed vertically between the BGA ball pads, aligned with the plating bath, with a hole center distance of 1 mm (Figures 9 and 10)
 
Figure 8: Unplated holes (slot separator)

Figure 9: Plating tank aligned with non-plated hole (slot separator)

Figure 10: Alignment with BGA pin footprint